Placement driven retiming with a coupled edge timing model

Retiming is a widely investigated technique for performance optimization. It performs powerful modifications on a circuit netlist. However, often it is not clear, whether the predicted performance improvement will still be valid after placement has been performed. This paper presents a new retiming algorithm using a highly accurate timing model taking into account the effect of retiming on capacitive loads of single wires as well as fanout systems. We propose the integration of retiming into a timing-driven standard cell placement environment based on simulated annealing. Retiming is used as an optimization technique throughout the whole placement process. The experimental results show the benefit of the proposed approach. In comparison with the conventional design flow based on standard FEAS our approach achieved an improvement in cycle time of up to 34% and 17% on the average

Convergence behaviour of structural FSM traversal

We present a theoretical analysis of structural FSM traversal, which is the basis for the sequential equivalence checking algorithm Record & Play presented earlier. We compare the convergence behaviour of exact and approximative structural FSM traversal with that of standard BDD-based FSM traversal. We show that for most circuits encountered in practice exact structural FSM traversal reaches the fixed point as fast as symbolic FSM traversal, while approximation can significantly reduce in the number of iterations needed. Our experiments confirm these results

Tight coupling of timing driven placement and retiming

Retiming is a widely investigated technique for performance optimization. In general, it performs extensive modifications on a circuit netlist, leaving it unclear, whether the achieved performance improvement will still be valid after placement has been performed. This paper presents an approach for integrating retiming into a timing-driven placement environment. The experimental results show the benefit of the proposed approach on circuit performance in comparison with design flows using retiming only as a pre- or postplacement optimization method

Verification of integer multipliers on the arithmetic bit level

One of the most severe short-comings of currently available equivalence checkers is their inability to verify integer multipliers. In this paper, we present a bit level reverse-engineering technique that can be integrated into standard equivalence checking flows. We propose a Boolean mapping algorithm that extracts a network of half adders from the gate netlist of an addition circuit. Once the arithmetic bit level representation of the circuit is obtained, equivalence checking can be performed using simple arithmetic operations. Experimental results show the promise of our approach

Accelerating Boolean implications with FPGAs

We present the FPGA implementation of an algorithm [4] that computes implications between signal values in a boolean network. The research was performed as a masterrsquos thesis [5] at the University of Frankfurt. The recursive algorithm is rather complex for a hardware realization and therefore the FPGA implementation is an interesting example for the potential of reconfigurable computing beyond systolic algorithms. A circuit generator was written that transforms a boolean network into a network of small processing elements and a global control logic which together implement the algorithm. The resulting circuit performs the computation two orders of magnitudes faster than a software implementation run by a conventional workstation

LOT: Logic Optimization with Testability - new transformations for logic synthesis

A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random pattern testability. The method is based on structural transformations at the gate level. New transformations involving EX-OR gates as well as Reed–Muller expansions have been introduced in the synthesis of multilevel circuits. This method is augmented with transformations that specifically enhance random-pattern testability while reducing the area. Testability enhancement is an integral part of our synthesis methodology. Experimental results show that the proposed methodology not only can achieve lower area than other similar tools, but that it achieves better testability compared to available testability enhancement tools such as tstfx. Specifically for ISCAS-85 benchmark circuits, it was observed that EX-OR gate-based transformations successfully contributed toward generating smaller circuits compared to other state-of-the-art logic optimization tools

The role of the chemokine CCL22 in the interaction of dendritic cells and regulatory T cells

Immune tolerance by regulatory T cells (TReg) requires continuous interactions with dendritic cells (DCs) to screen the organism for potentially harmful self-antigen presentation. Ultimately, this interaction keeps effector T cells (TEff) with auto-reactive properties in check as the contact with DCs, TReg and cognate antigen induces anergy, a state of non-responsiveness. The efficient collaboration of these three immune cell types therefore dictates the delicate balance between immunity and tolerance. The aim of this study was to investigate the role of the chemokine CCL22 as a mediator of DC-TReg interactions. Based on previous observations of CCL22-dependent migration of CCR4+ TReg and CCL22 production by DCs, we hypothesized that CCL22 recruits TReg to DCs and increases their interaction frequency. Therefore, I investigated DC-TReg interactions in vitro and in vivo. In addition, I studied the influence of innate and adaptive immune stimulation on CCL22 and CCR4 expression. I showed that DC-TReg interactions were significantly more frequent in vitro and in vivo for DCs that secreted CCL22 compared to DCs that did not secrete CCL22. In vivo, I studied dynamic interactions in peripheral lymph nodes by intravital microscopy and observed longer antigen-dependent DC-TReg contact times for DCs that secreted CCL22. These results suggest that the homeostatic production of CCL22 by DCs serves as a signal to recruit TReg to support continuous immune tolerance during the steady state. Studying the influence of the innate immune system on the CCL22-CCR4 axis, I observed a decrease of CCR4 expression by TReg after stimulation with TLR and RLR ligands. In contrast, adaptive immune responses in the form of cognate-antigen DC-TEff interactions led to strong and rapid induction of CCR4 expression by TReg and further to CCL22 production by DCs. This strong induction following cognate-antigen interaction with TEff might represent a mechanism of immune surveillance, as more TReg will be recruited to the DCs that interact with TEff. These new mechanistic insights advance our comprehension of TReg function and may help to make use of their enormous potential in clinical applications for autoimmune diseases, for cancer and beyond

Cell replication and redundancy elimination during placement for cycle time optimization

This paper presents a new timing driven approach for cell replication tailored to the practical needs of standard cell layout design. Cell replication methods have been studied extensively in the context of generic partitioning problems. However, until now it has remained unclear what practical benefit can be obtained from this concept in a realistic environment for timing driven layout synthesis. Therefore, this paper presents a timing driven cell replication procedure, demonstrates its incorporation into a standard cell placement and routing tool and examines its benefit on the final circuit performance in comparison with conventional gate or transistor sizing techniques. Furthermore, we demonstrate that cell replication can deteriorate the stuck-at fault testability of circuits and show that stuck-at redundancy elimination must be integrated into the placement procedure. Experimental results demonstrate the usefulness of the proposed methodology and suggest that cell replication should be an integral part of the physical design flow complementing traditional gate sizing techniques